See Asm8051 for general information and ReverseFirmware for all pages

check http://www.designtools.co.nz/ and its overview of C51 vendors (there's ADI)

IDATA=0x80
no XDATA memory
no PDATA memory

interrupt :
0x13 (eagleI only)
0x33
0x43 : jump table to another interrupt table for usb int
0x4b
0x63

for cypress we have :

New 8051 Interrupt (IRQ name) Source Vector Priority
X TF2 Timer 2 Overflow 2B 6
X Resume (WAKEUP) WAKEUP# Pin or USB Core 33 0
X RI_1 & TI_1 UART1 Rx & Tx 3B 7
X USB (INT2) USB Core 43 8
X USB Core 4B 9
X IE4 (FIFOs) Slave FIFOs/INT4 pin 53 10
X IE5 INT5# Pin 5B 11
X IE6 INT6 Pin 63 12


jump table (eagleI):
0x0
0x4
0x8
0xc
0x10
0x14 : void
[...]
0x54 : void

We have 21 possible interrupts like cypress :

starting

The processor start @0
Because @3 we have interrupt table,we need to jump somewhere.
Clear IDATA memory with 0
set stack pointer (sp)
jump to C code

dma

1)
DMADEST <- IN2BUF0 (AUTOPTR)
DMASRC <- DMAEXTFIFO
DMALEN <- 0x40

2)
DMADEST <- IN2BUF0
DMASRC <- DMAEXTFIFO
DMALEN <- 0x40

3)
DMADEST <- IN8DATA (iso data address)
DMASRC <- DMAEXTFIFO
DMALEN <- 0x35

4)
DMADEST <- DMAEXTFIFO
DMASRC <- OUT2BUF0
DMALEN <- OUT2BC

4b) (idma transfert)
DMADEST <- DMAEXTFIFO
DMASRC <- OUT4BUF0
DMALEN <- si pm 0x3f moins ou val si dm

5)
DMADEST <- 0x3f40
DMASRC <- DMAEXTFIFO
DMALEN <- 0x40

6)
DMADEST <- IN2BUF0
DMASRC <- 0x3f40
DMALEN <- 0x40

7)
DMADEST <- 0x3f40
DMASRC <- DMAEXTFIFO
DMALEN <- 0x40

hardware connection

From http://www.analog.com/UploadedFiles/Data_Sheets/26988897222791524014637367292314678ADSP_218xN_0.pdf

D23-8 isn't idma specific.

IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is as-
serted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address spec-
ifies an on-chip memory location, the destination type spec-
ifies whether it is a DM or PM access. The falling edge of
the IDMA address latch signal (IAL) or the missing edge of
the IDMA select signal (IS) latches this value into the
IDMAA register.
Once the address is stored, data can be read from, or written
to, the ADSP-218xN's on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD
and IWR respectively) signals the ADSP-218xN that a par-
ticular transaction is required. In either case, there is a one-
processor-cycle delay for synchronization. The memory
access consumes one additional processor cycle.

DMAEXTFIFO use the 8051 databus with FRD# and FRW# use as strobe.

We could guess that
- 8051 databus is connected to IAD15-0 bus (we should make sure to put 8051 in 16 bit mode bus)
- 8051 FRD# is connected to IRD
- 8051 FWD# is connected to IWD

The big question is how we select an address on the adsp.
An how the adsp interrupt (int6???) the 8051 for requesting other overlays.

Some communication is performed by 8051 PORT bits and some by memory mapped registers at space >= 0x4000 (0x4800 for eagleII)

output bit 0x90 (IOB.0) is IS or IAL
output bit 0x91 (IOB.1) is IAL or IS
input bit 0xb3 (IOD.3) is IACK

Writing Data Memory through DMEEXTFIFO need set up bit 4 at 0x4000 (0x4800 for eagle2) for writing Program Memory clear this bit.
Propably this indicate how external fifo threat data: 16bit words or special 24bit.

Additionally allways before operating on IDMA bit IOB.4 is setted up, old value is saved and restored after idma address latch transfer.
This bit sync access with DSP or put IWR and IRD lines in inactive state, as needed for proper address latch, other purposes are possible
as well.

Seems IDMAA and IDMAoverlay registers are accessed at 16bit register 0x4001 | 0x4002 (+0800 for eagle2)

IDMA is used for two purposes

• Boot
• Data transfer

For Boot we don't need to sync access wit DSP, however need reset DSP and put them in boot mode, which bits are used for this?

For Data transfer we need sync with DSP. Propably dsp only program IDMA address/overlay and give info to 8051 when IDMA is ready.
Seems bit 0x87 (IOA.7) mean: "IDMA ready for down stream data" and bit 0x97 (IOB.7) mean "ready for up stream".
However two bit communication is too simple and propably other bits are used for sync.

port

PORTACFG=0
PORTBCFG=0
PORTCCFG=0
IFCONFIG=0
PORTSETUP=1 (sfr port)
PORTACF2=0

SOEA=0xff (all output)
at init IOA=1<<4 | 1<<3
temp value for IOA are in 0x2e

SOEB=0xff (all output)
at init IOB=0 (pin 2 and 3 used, pin 4 cleared)
temp value for IOB are in 0x2f

SOEC=0xff (all output)
at init : pin0, pin4, pin5 set, pin1, pin2, pin3 cleared
temp value for IOC are in 0x30

SOED=0xff (all output)
at init : pin0, pin1, pin2, pin3, pin4 set
temp value for IOD are in 0x31

at init SOEE=0x40 (pin6) and pin6 set to 0.
SOEE is changed in the code...
temp value for IOE are in 0x32

others values

USBBAV=1 (!INT2SFC !BREAK !BPPULSE !BPEN AVEN)
USBIEN=0x1f (!IBNIE URESIE SUSPIE SUTOKIE SOFIE SUDAVIE)
EIE=0x10 : enable int6 that is connected to pin6 of port b.

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